The present specification relates to a semiconductor device comprising a pn junction diode and a method of making a semiconductor device comprising a pn junction diode.
In advanced fully-depleted silicon-on-insulator (FDSOI) technologies, while most of active devices (e.g. Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)) are built on an SOI region where the insulator is a buried oxide layer, active devices with high current and high voltages (e.g. Laterally Diffused Metal Oxide Semiconductor Field Effect Transistors (LDMOS), PN junction diodes) are constructed on a non-SOI region (i.e. on a conventional bulk substrate, which may be called a HYBRID region, where the buried oxide layer has been removed). The reverse-bias junction breakdown voltage is one of the key Figure of Merit (FoM) for these devices.
FIG. 1 shows an example of a pn junction diode 10. The diode includes a semiconductor substrate 2, which may be a p-type substrate. An n-well 4 is located on the substrate 2. A p-type (P+) region 14 forms a first electrode (the cathode) of the diode 10. The other electrode (the anode) of the diode 10 is formed by n-type regions 12. The electrodes 12, 14 are separated by isolation regions 6.
In a device of the kind shown in FIG. 1, the pn junction is located at the interface between the underside of a p-type region 14 and the n-well 4. The point at which the highest electric field occurs in such a device (and therefore the point at which breakdown occurs—indicated at 20 in FIG. 1) is therefore located deep in the substrate (i.e. away from the silicon surface). In such a device the breakdown voltage is simply determined by the junction doping between the p-type region 14 and the n-well 4. This diode is a vertical device.